Methods of forming conductive contacts

ABSTRACT

Methods of forming conductive contacts are described. According to one implementation, the method includes forming a transistor gate structure over a substrate. The gate structure includes a conductive silicide covered by insulative material. A dielectric layer is formed over the substrate and the gate structure. A contact opening is etched into the dielectric layer adjacent the gate structure. After the etching, the substrate is exposed to oxidizing conditions effective to oxidize any conductive silicide within the contact opening which was exposed during the contact opening etch. After the oxidizing, conductive material is formed within the contact opening. According to another embodiment, after the etching, it is determined whether conductive silicide of the gate structure was exposed during the etching. The substrate is then exposed to oxidizing conditions only if conductive silicide of the gate structure was exposed during the etching.

TECHNICAL FIELD

[0001] This invention relates to methods of forming conductive contacts.

BACKGROUND OF THE INVENTION

[0002] In semiconductor wafer fabrication, conductive contacts aretypically made between different device components and conductive lines.One particular aspect of one form of semiconductor processing, andproblems associated therewith, is described with reference to FIGS. 1-3.FIG. 1 depicts a semiconductor wafer fragment 10 comprised of a bulkmonocrystalline silicon substrate 12 having a trench isolation region 14formed therein. Isolation region 14 typically comprises a silicondioxide comprising material. In the context of this document, the term“layer” refers to both the singular and plural. Further, in the contextof this document, the term “semiconductive substrate” or “semiconductorsubstrate” is defined to mean any construction comprising semiconductivematerial, including, but not limited to, bulk semiconductive materialssuch as a semiconductive wafer (either alone or in assemblies comprisingother materials thereon), and semiconductive material layers (eitheralone or in assemblies comprising other material). The term “substrate”refers to any supporting structure, including, but not limited to, thesemiconductive substrates described above.

[0003] Wafer fragment 10 comprises a field effect transistor gatestructure 16 having source/drain regions 17 and 18 formed withinsubstrate 12. Transistor gate structure 16 comprises a gate dielectriclayer 20, an overlying conducively doped polysilicon layer 22, anoverlying conductive silicide region 23 and an overlying insulative cap24. Exemplary materials for gate dielectric layer 20 includes silicondioxide, for silicide layer 23 tungsten silicide, and for insulative cap24 silicon nitride. Anisotropically etched sidewall spacers 25 areformed laterally about sidewalls of transistor gate structure 16.

[0004] An etch stop layer 26 is formed over transistor gate structure 16and substrate 12/14. Exemplary typical materials include undoped silicondioxide, silicon nitride or a silicon oxynitride. The typical thicknessof the etch stop layer 26 is 300 Å, with a preferred range of thicknessbeing from 150 Å to 1000 Å. A planarized insulative dielectric layer 28,for example borophosphosilicate glass (BPSG), is provided over etch stoplayer 26.

[0005] Referring to FIG. 2, a contact opening 30 has been etched throughinsulative dielectric layer 28 to substrate 12. Such would typically beconducted by photolithographic processing providing a layer ofphotoresist and a mask opening therethrough which provides the exposedarea of material 28 for the etch. The illustrated etch is typicallyreferred to as a self-aligned-contact etch as the materials of circuitryconstruction and the etch chemistry is intended to be largely selectiveto etch material 28 without necessarily etching transistor gatestructure 16 and etch stop layer 26 thereover. The illustrated prior artprocessing would typically etch material 28 in a manner which isintended to be highly selective to stop at etch stop layer 26, and etchstop layer 26 would thereafter be etched to provide exposure tosource/drain region 18. Tungsten suicide typically etches faster thansilicon.

[0006] Although intended to be highly selective and self-aligning, incertain instances the exposed spacer 25 and perhaps some of theinsulative cap 24 might be etched as shown to provide some exposure ofconductive silicide region 23. Referring to FIG. 3, this is highlyundesirable as contact opening 30 is typically ultimately plugged with aconductive material 32 which undesirably creates a fatal short to theconductive silicide of the gate structure.

[0007] The invention was principally motivated in overcoming theabove-identified problem. However the invention is in no way so limited,and is only limited by the accompanying claims as literally worded andappropriately interpreted in accordance with the Doctrine ofEquivalents.

SUMMARY OF THE INVENTION

[0008] Methods of forming conductive contacts are described. Accordingto one implementation, the method includes forming a transistor gatestructure over a substrate. The gate structure includes a conductivesilicide covered by insulative material. A dielectric layer is formedover the substrate and the gate structure. A contact opening is etchedinto the dielectric layer adjacent the gate structure. After theetching, the substrate is exposed to oxidizing conditions effective tooxidize any conductive suicide within the contact opening which wasexposed during the contact opening etch. After the oxidizing, conductivematerial is formed within the contact opening.

[0009] According to one implementation, the method includes forming atransistor gate structure over a substrate. The gate structure includesa conductive suicide covered by insulative material. A dielectric layeris formed over the substrate and the gate structure. A contact openingis then etched into the dielectric layer adjacent the gate structure.After the etching, it is determined whether conductive silicide of thegate structure was exposed during the etching. If it is determined thatconductive silicide of the gate structure was exposed during theetching, the exposed silicide within the contact opening is oxidizedeffective to form an insulative isolation mass within the contactopening on the conductive silicide. After the oxidizing, conductivematerial is formed within the contact opening and on the insulativeisolation mass. If it is determined that conductive silicide of the gatestructure was not exposed during said etching, conductive material isformed within the contact opening without conducting said oxidizing.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0011]FIG. 1 is a diagrammatic sectional view of a prior artsemiconductor wafer fragment at one prior art processing step.

[0012] FIG.2 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 1.

[0013]FIG. 3 is a view of the FIG. 2 wafer fragment at a processing stepsubsequent to that shown by FIG. 2.

[0014]FIG. 4 is a diagrammatic sectional view of a semiconductor waferfragment at one processing step in accordance with one aspect of theinvention.

[0015]FIG. 5 is a view of the FIG. 4 wafer fragment at a processing stepsubsequent to that shown by FIG. 4.

[0016]FIG. 6 is a view of the FIG. 5 wafer fragment at a processing stepsubsequent to that shown by FIG. 5.

[0017]FIG. 7 is a view of the FIG. 6 wafer fragment at a processing stepsubsequent to that shown in FIG. 6.

[0018]FIG. 8 is a diagrammatic sectional view of an alternate embodimentsemiconductor wafer fragment at one processing step.

[0019]FIG. 9 is a view of the FIG. 8 wafer fragment at a processing stepsubsequent to that shown by FIG. 8.

[0020]FIG. 10 is a view of the FIG. 9 wafer fragment at a processingstep subsequent to that shown by FIG. 9.

[0021]FIG. 11 is a view of the FIG. 10 wafer fragment at a processingstep subsequent to that shown by FIG. 10.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0023] A first preferred embodiment method of forming a conductivecontact is described initially with reference to FIGS. 4-7. Referring toFIG. 4, a wafer fragment 35 comprises a bulk substrate 36 and anisolation region 38 formed therein. Bulk monocrystalline silicon is apreferred material for substrate 36, while a preferred isolation region38 comprises a trench isolation region formed in part by filling withhigh density plasma deposited oxide. A transistor gate structure 40 isformed over substrate 36. Laterally opposing source/drain regions 41 areformed within substrate 36 relative to opposing sides of transistor gatestructure 40.

[0024] Transistor gate structure 40 comprises a gate dielectric layer42, a conducively doped polysilicon layer 44, and a conductive silicidelayer 46. But one example conductive silicide is WSi_(X). StoichiometricWSi₂ is one specific example. However, utilizing silicon-rich tungstensilicide, or other silicon-rich silicides, is more preferred. Specificexamples include “x” being greater than 2 and less than 3, with 2.5being a more specific example. The conductive silicide is preferablycovered by insulative material. In the illustrated and preferredembodiment, the insulative material is in part provided in the form ofan insulative cap 48 which is formed on (in contact with) conductivesilicide 46, and has the same approximate lateral dimensions asconductive silicide layer 46 and polysilicon layer 44. The preferredembodiment wafer fragment 35 also is shown to include opposingrespective insulative sidewall spacers 50 and 51. For purposes of thecontinuing discussion, sidewall spacer 51 can be considered as having aninitial height “A”. A dielectric layer or insulative material 42 isformed over substrate 36/38 and gate structure 40. Such layer is alsopreferably planarized, with preferred planarization techniques beingre-flow or CMP. Exemplary materials for layer 42 are BPSG or PSG.

[0025] The illustrated and described preferred transistor gate structure40 comprises but one preferred embodiment gate structure fabricated inaccordance with methodical aspects of the invention. Any othertransistor gate structure is contemplated, whether existing or yet-to-bedeveloped, in accordance with the invention as long as such includes atleast a conductive silicide which is at some point covered by insulativematerial regardless of whether such insulative material contacts thesubject silicide.

[0026] Referring to FIG. 5, a contact opening 52 is etched intodielectric layer 42 adjacent gate structure 40 effective to exposeconducive silicide 46 of gate structure 40. In the depicted preferredembodiment, such etching is also effective to expose insulative cap 48and insulative sidewall spacer 51. Further in the illustrated preferredembodiment, insulative sidewall spacer 51 has also been etchedeffectively reducing its initial height “A”, and a portion of insulativecap 48 is also shown as being etched.

[0027] Referring to FIG. 6, the exposed silicide of silicide layer 46 isexposed to oxidizing conditions effective to oxidize it within contactopening 52, and effective to form an insulative isolation mass 56 withincontact opening 52 on conductive silicide 46. An oxide layer 57 willalso tend to form upon semiconductive material of substrate 36.Insulative isolation mass 56 is characterized by, or of, a sufficientthickness to prevent undesirable electrical contact between conductivesilicide 46 and conductive material which will be received withincontact opening 52. In one preferred embodiment, the oxidizingconditions are effective to form insulative isolation mass 56 to have aminimum thickness of at least 50 Å. In the context of this document,“minimum thickness” refers to the shortest straight linear dimensionfrom conductive silicide material 46 and conductive material ultimatelyprovided within contact opening 52. Insulative isolation mass 46 can beformed to other greater alternate minimum thicknesses, for example of atleast 100 Å, or of at least 150 Å, or greater.

[0028] Any suitable oxidizing conditions can be utilized effective toform an insulative isolation mass as herein defined. By way of exampleonly, example dry oxidation conditions include 800° C., ambientpressure, O₂ flow at 6 slm, and N₂ flow at 30 slm. Further by way ofexample only, exemplary wet oxidation conditions include 800° C.,ambient pressure, N₂ flow at 30 slm, O₂ flow at 8.0 slm, H₂ flow at 2slm.

[0029] After the oxidizing, a preferred short punch dry etch isconducted to remove at least some, and preferably all, of oxide layer 57from within contact opening 52. Some, but not all, of oxide mass 56might also be removed during such etching. Exemplary preferredconditions include remote plasma etching, power at 400 Watts, susceptortemperature of 45 degrees C., pressure of 200 mTorr, CHF3 flow of 60sccm and CF4 flow of 60 sccm. An exemplary time for the etching is from5 seconds to 20 seconds, with lower times being preferred.

[0030] Referring to FIG. 7, conductive material 58 is formed withincontact opening 52. Such might include a single or multiple materialsincluding silicide, glue layers, diffusion barrier materials, etc. Inthe depicted and preferred embodiment, conductive material 58 is formedto completely fill a contact opening 52.

[0031] But one exemplary alternate embodiment is described withreference to FIGS. 8-11 with respect to a wafer fragment 35 a. Likenumerals from the first described embodiment are utilized whereappropriate, with differences being indicated by the suffix “a” or withdifferent numerals. Referring to FIG. 8, such corresponds in processingsequence to FIG. 5 of the first described embodiment. Such differs fromthe first described embodiment in the provision of an etch stop layer 62over substrate 36/38 and transistor gate structure 40. Exemplarypreferred materials for etch stop layer 62 are as described above in the“Background” section of this document. FIG. 8 depicts less than desiredprocessing whereby the etching to form contact opening 52 has alsoetched a portion of etch stop layer 62 effective to expose a portion ofconductive silicide 46.

[0032] Referring to FIG. 9, wafer fragment 35a has been exposed tosuitable oxidizing conditions effective to oxidize exposed silicidewithin contact opening 52 to form insulative isolation mass 56.

[0033] Referring to FIG. 10, at least a portion of etch stop layer 62has been etched through within contact opening 52 after oxidizing theexposed silicide effective to form isolation mass 56. By way of exampleonly, and where etch stop layer 62 comprises a silicon oxynitride, achemistry effective to do the same comprises a combination of CHF₃ andCF₄. A dry punch etch as described above might also be conducted.

[0034] Referring to FIG. 11, conductive material 58 is formed withincontact opening 52.

[0035] The above-described first preferred embodiments depict ordescribe methods wherein conductive silicide is exposed during theetching to form contact opening 52. However regardless of whetherconductive silicide is exposed during the contact opening etching, theinvention contemplates exposing the substrate to oxidizing conditionseffective to oxidize any conductive silicide within the contact openingwhich might have been exposed during the contact opening etch. Forexample, the contact opening etching may or may not expose conductivesilicide. Regardless, the substrate can be exposed to oxidizingconditions effective to oxidize any such silicide that was exposed toinsure that an effective isolation mass is formed on any exposedsilicide without necessarily verifying the presence of the same prior toconducting the oxidizing.

[0036] In another aspect, the invention contemplates conducting anactual determination to see if conductive silicide of the gate structurewas exposed during the contact opening etching. Such could of course beconducted by some visual inspection with scanning electron microscope,or by other existing or yet-to-be developed methods. Regardless, if thedetermining were to reveal that conductive silicide of the gatestructure was exposed during the etching, the exposed suicide within theeffected contact openings could be oxidized effective to form thedesired insulative isolation masses within the contact openings on theconductive silicide. Thereafter, conductive material would be formedwithin the contact openings and on the formed insulative isolationmasses. If the determining reveals that conductive silicide of the gatestructures were not exposed during the etching, conductive materialcould be formed within the contact openings without conducting thesubject oxidizing.

[0037] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming a conductive contact comprising: forming atransistor gate structure over a substrate, the gate structurecomprising a conductive silicide covered by insulative material; forminga dielectric layer over the substrate and the gate structure; etching acontact opening into the dielectric layer adjacent the gate structure;after the etching, exposing the substrate to oxidizing conditionseffective to oxidize any conductive silicide within the contact openingexposed during the contact opening etch; and after the oxidizing,forming conductive material within the contact opening.
 2. The method offorming a conductive contact of claim 1, wherein the conductive silicideis WSi_(X).
 3. The method of forming a conductive contact of claim 1,wherein the conductive silicide is silicon rich in comparison tostoichiometric silicide.
 4. The method of forming a conductive contactof claim 1, wherein the forming of the gate structure comprises formingan insulative sidewall spacer on at least one side of the gatestructure, the etching exposing the insulative sidewall spacer.
 5. Themethod of forming a conductive contact of claim 1, wherein the formingof the gate structure comprises forming an insulative sidewall spacer onat least one side of the gate structure, the insulative sidewall spacerhaving a height, the etching exposing the insulative sidewall spacer andreducing the height.
 6. The method of forming a conductive contact ofclaim 1, wherein the forming of the gate structure comprises forming aninsulative sidewall spacer on each side of the gate structure.
 7. Themethod of forming a conductive contact of claim 1, wherein the formingof the gate structure comprises forming an insulative sidewall spacer onat least one side of the gate structure and forming an insulative cap onthe conductive silicide, the etching exposing the insulative sidewallspacer.
 8. The method of forming a conductive contact of claim 1,wherein the forming of the gate structure comprises forming aninsulative sidewall spacer on each side of the gate structure andforming an insulative cap on the conductive silicide.
 9. The method offorming a conductive contact of claim 1, wherein the conductive silicideis WSi_(X), and wherein conductive silicide is exposed during theetching, and wherein the oxidizing conditions are effective to form aninsulative isolation mass of a sufficient thickness to preventundesirable electrical contact between the conductive silicide and theconductive material formed within the contact opening.
 10. The method offorming a conductive contact of claim 9, wherein the oxidizingconditions are effective to form the insulative isolation mass to aminimum thickness of at least 50 Angstroms.
 11. The method of forming aconductive contact of claim 9, wherein the oxidizing conditions areeffective to form the insulative isolation mass to a minimum thicknessof at least 100 Angstroms.
 12. The method of forming a conductivecontact of claim 9, wherein the oxidizing conditions are effective toform the insulative isolation mass to a minimum thickness of at least150 Angstroms.
 13. The method of forming a conductive contact of claim9, wherein after forming the transistor gate structure and beforeforming the dielectric layer, forming an etch stop layer over thesubstrate and the gate structure.
 14. The method of forming a conductivecontact of claim 13, wherein the etch stop layer is electricallyinsulative, and further comprising etching through at least a portion ofthe etch stop layer within the contact opening after the oxidizing. 15.The method of claim 1 wherein the substrate comprises semiconductivematerial and the oxidizing conditions oxidize at least some of thesemiconductive material, the method further comprising etching at leastsome of the oxidized semiconductive material from the contact openingprior to forming the conductive material therewithin.
 16. A method offorming a conductive contact, comprising: forming a transistor gatestructure over a substrate, the gate structure comprising a conductivesilicide covered by insulative material; forming a dielectric layer overthe substrate and the gate structure; etching a contact opening into thedielectric layer adjacent the gate structure effective to expose theconductive silicide of the gate structure; after the etching, oxidizingthe exposed silicide within the contact opening effective to form aninsulative isolation mass within the contact opening on the conductivesilicide; and after the oxidizing, forming conductive material withinthe contact opening and on the insulative isolation mass.
 17. The methodof forming a conductive contact of claim 16, wherein the conductivesilicide is WSi_(X).
 18. The method of forming a conductive contact ofclaim 16, wherein the conductive silicide is silicon rich in comparisonto stoichiometric silicide.
 19. The method of forming a conductivecontact of claim 16, wherein the forming of the gate structure comprisesforming an insulative sidewall spacer on at least one side of the gatestructure, the etching exposing the insulative sidewall spacer.
 20. Themethod of forming a conductive contact of claim 16, wherein the formingof the gate structure comprises forming an insulative sidewall spacer onat least one side of the gate structure, the insulative sidewall spacerhaving a height, the etching exposing the insulative sidewall spacer andreducing the height.
 21. The method of forming a conductive contact ofclaim 16, wherein the forming of the gate structure comprises forming aninsulative sidewall spacer on at least one side of the gate structureand forming an insulative cap on the conductive silicide, the etchingexposing the insulative sidewall spacer.
 22. The method of forming aconductive contact of claim 16, wherein the insulative isolation mass isformed to a minimum thickness of at least 50 Angstroms.
 23. The methodof forming a conductive contact of claim 16, wherein the insulativeisolation mass is formed to a minimum thickness of at least 100Angstroms.
 24. The method of forming a conductive contact of claim 16,wherein the insulative isolation mass is formed to a minimum thicknessof at least 150 Angstroms.
 25. The method of forming a conductivecontact of claim 16, wherein after forming the transistor gate structureand before forming the dielectric layer, forming an etch stop layer overthe substrate and the gate structure.
 26. The method of forming aconductive contact of claim 25, comprising etching through at least aportion of the etch stop layer within the contact opening afteroxidizing the exposed silicide.
 27. The method of claim 16 wherein thesubstrate comprises semiconductive material and the oxidizing oxidizesat least some of the semiconductive material, the method furthercomprising etching at least some of the oxidized semiconductive materialfrom the contact opening prior to forming the conductive materialtherewithin.
 28. A method of forming a conductive contact, comprising:forming a transistor gate structure over a substrate, the gate structurecomprising a conductive silicide covered by insulative material; forminga dielectric layer over the substrate and the gate structure; etching acontact opening into the dielectric layer adjacent the gate structure;after the etching, determining if conductive silicide of the gatestructure was exposed during said etching; if the determining revealsconductive silicide of the gate structure was exposed during saidetching, i) oxidizing the exposed silicide within the contact openingeffective to form an insulative isolation mass within the contactopening on the conductive silicide; and ii) after the oxidizing, formingconductive material within the contact opening and on the insulativeisolation mass; and if the determining reveals conductive silicide ofthe gate structure was not exposed during said etching, formingconductive material within the contact opening without conducting saidoxidizing.
 29. The method of forming a conductive contact of claim 28,wherein the conductive silicide is WSi_(X).
 30. The method of forming aconductive contact of claim 28, wherein the conductive silicide issilicon rich in comparison to stoichiometric silicide.
 31. The method offorming a conductive contact of claim 28, wherein the forming of thegate structure comprises forming an insulative sidewall spacer on atleast one side of the gate structure, the etching exposing theinsulative sidewall spacer.
 32. The method of forming a conductivecontact of claim 28, wherein the a forming of the gate structurecomprises forming an insulative sidewall spacer on at least one side ofthe gate structure and forming an insulative cap on the conductivesilicide, the etching exposing the insulative sidewall spacer.
 33. Themethod of forming a conductive contact of claim 28, wherein afterforming the transistor gate structure and before forming the dielectriclayer, forming an etch stop layer over the substrate and the gatestructure.
 34. The method of forming a conductive contact of claim 28,comprising etching through at least a portion of the etch stop layerwithin the contact opening after oxidizing the exposed silicide.
 35. Amethod of forming a conductive contact, comprising: forming a transistorgate structure over a substrate, the gate structure comprising aconductive silicide, opposing insulative sidewall spacers, and aninsulative cap on the conductive silicide; forming a dielectric layerover the substrate and the gate structure; etching a contact openinginto the dielectric layer adjacent the gate structure, and exposing theinsulative cap and one of the sidewall spacers within the contactopening; after the etching, exposing the substrate to oxidizingconditions effective to oxidize any conductive silicide within thecontact opening exposed during the contact opening etch; and after theoxidizing, forming conductive material within the contact opening. 36.The method of forming a conductive contact of claim 35, wherein theconductive silicide is WSi_(X).
 37. The method of forming a conductivecontact of claim 35, wherein the conductive silicide is silicon rich incomparison to stoichiometric silicide.
 38. The method of forming aconductive contact of claim 35, wherein conductive silicide is exposedduring the etching, and wherein the oxidizing conditions are effectiveto oxidize the exposed conductive silicide to form an insulativeisolation mass to a minimum thickness of at least 50 Angstroms.
 39. Themethod of forming a conductive contact of claim 35, wherein afterforming the transistor gate structure and before forming the dielectriclayer, forming an etch stop layer over the substrate and the gatestructure.
 40. The method of forming a conductive contact of claim 39,wherein the method further comprises etching through at least a portionof the etch stop layer within the contact opening after the oxidizing.41. The method of claim 35 wherein the substrate comprisessemiconductive material and the oxidizing conditions oxidize at leastsome of the semiconductive material, the method further comprisingetching at least some of the oxidized semiconductive material from thecontact opening prior to forming the conductive material therewithin.42. A method of forming a conductive contact, comprising: forming atransistor gate structure over a substrate, the gate structurecomprising a conductive silicide having an insulative sidewall spacer,and having an insulative cap on the conductive silicide; forming an etchstop layer over the substrate and the gate structure; after forming theetch stop layer, forming a dielectric layer over the substrate and thegate structure; etching a contact opening into the dielectric layeradjacent the gate structure effective to expose the conductive silicideof the gate structure; after the etching, oxidizing the exposedconductive silicide within the contact opening effective to form aninsulative isolation mass within the contact opening on the conductivesilicide; and after the oxidizing, forming conductive material withinthe contact opening and on the insulative isolation mass.
 43. The methodof forming a conductive contact of claim 42, wherein the conductivesilicide is WSi_(X)
 44. The method of forming a conductive contact ofclaim 42, wherein the conductive silicide is silicon rich in comparisonto stoichiometric silicide.
 45. The method of forming a conductivecontact of claim 42, wherein the forming of the gate structure comprisesforming an insulative sidewall spacer on each side of the gatestructure.
 46. The method of forming a conductive contact of claim 42,wherein the insulative isolation mass is formed to a minimum thicknessof at least 50 Angstroms over the exposed conductive silicide.
 47. Themethod of claim 42 wherein the substrate comprises semiconductivematerial and the oxidizing oxidizes at least some of the semiconductivematerial, the method further comprising etching at least some of theoxidized semiconductive material from the contact opening prior toforming the conductive material therewithin.